1. Field of the Invention
The present invention relates to a large-scale integrated-circuit apparatus, particularly to a large-scale integrated-circuit apparatus comprising a plurality of circuits to be initialized when an electrical power source is turned on.
An application specific integrated circuit (hereafter referred to as ASIC) has been developed so far which is not a general-purpose IC such as a CPU or a memory but an IC for realizing a function most suitable for a specific purpose.
Because the semiconductor-integrated-circuit art has been recently developed, the operation speed, integration degree, and scale of the ASIC of this type have been improved and moreover, each circuit constituting the ASIC has been developed from a circuit having a single function to a circuit having multiple functions.
2. Related Background Art
In the case of an ASIC, at least three types of circuits such as a CPU, a peripheral logic circuit, and an application specific logic circuit have been independently improved in integration degree, operation speed, and scale. However, because the semiconductor-integrated-circuit art for a one-chip configuration including every function in the same chip has been recently established, further-advanced integration is realized. Also in the case of an ASIC, a CPU, a peripheral logic circuit, and an application specific logic circuit are integrated on one semiconductor wafer by the semiconductor-integrated-circuit art for realizing a one-chip configuration.
The above semiconductor integrated circuit greatly advanced in integration samples an external input signal in accordance with an external clock signal and captures it. Moreover, an internal circuit operates by converting an external clock signal into a sync signal.
As described above, in the case of a conventional BASIC advanced in integration, though a plurality of circuits mounted on a semiconductor wafer respectively synchronize with an external clock signal, each circuit only independently functions.
That is, though a circuit operation synchronizes with a clock, the reset operation (initialization) of each circuit when an electrical power source is turned on is independently performed. Therefore, a slight difference occurs between reset timings of the circuits and this makes operations of an ASIC unstable.
The above mentioned is described below by referring to FIG. 11 showing a block diagram of a conventional ASIC. Symbol 101 denotes an ASIC. A CPU 102, a peripheral logic circuit 103, and an application specific logic circuit 104 are set in the ASIC 101. The peripheral logic circuit 103 controls transfer of data between a memory (not shown) built in the ASIC 101, a program ROM (not shown) set to the outside of the ASIC 101, and the application specific logic circuit 104 on one hand and the CPU 102 on the other. The application specific logic circuit 104 is a logic circuit to be set to a specific control unit on which the ASIC 101 is mounted by a user in order to optimize the ASIC 101.
Symbol 105 denotes a clock signal supplied from an external unit to the ASIC 101, which is used to synchronize internal circuits of the ASIC 101. Symbol 106 denotes a reset signal supplied from an external unit to the ASIC 101. Symbol 107 denotes an inverter circuit set in the ASIC 101 to logic-invert the reset signal 106.
In the case of the above conventional ASIC 101, when the reset signal 106 is input for a predetermined period in accordance with rise of an electrical power source, an internal reset signal 108 obtained by inverting the reset signal 106 is input to reset terminals of the CPU 102, peripheral logic circuit 103, and application specific logic circuit 104. The CPU 102, peripheral logic circuit 103, and application specific logic circuit 104 are initialized by receiving the internal reset signal 108.
However, because a difference occurs between rises of voltages of the CPU 102, peripheral logic circuit 103, and application specific logic circuit 104 after start of power supply, reset timings of the circuits 102, 103, and 104 are slightly different from each other. Therefore, the reset timing of the CPU 102 may be later than the reset timings of the peripheral logic circuit 103 and the application specific logic circuit 104. In this case, a problem occurs that stable operations of the ASIC 101 cannot be expected.
The present invention is made to solve the above problems and its object is to provide a large-scale integrated-circuit apparatus for controlling the reset timing of each circuit to a proper value when initializing a plurality of circuits constituting an ASIC.